1. Field of the Invention
The present invention relates to high-stability analog phase-locked loops with a digital processor employed for signal processing and control functions.
2. Description of Related Art
A phase-locked loop is designed to generate and maintain an internal reference signal in phase and frequency alignment with an external reference signal. Alignment is maintained by comparing the external reference signal to the internal reference signal to generate a phase error signal. The phase error signal is filtered to generate a control signal for adjusting the internal reference signal to minimize the phase error. In an environment which requires very accurate alignment, a phase-locked loop must have a filter with an extremely narrow bandwidth. A narrow bandwidth for the phase-locked loop results in a very narrow phase and frequency pull-in range. Thus, during start up or other times when the phase error is large, the phase-locked loop will be slow, or unable to adjust.
In previously known implementations of phase-locked loops, a wider pull-in range during start up is achieved either by initial manual frequency alignment or by use of a "pull-in" mode in which the parameters of the phase-locked loop are modified to provide a wider bandwidth. After initial lock-up in the pull-in mode, the phase-locked loop parameters are switched either manually or automatically to the narrow bandwidth required for high accuracy during operation.
The manual alignment method is inconvenient and expensive because it requires operator intervention in order to acquire a lock. The second method involving the automatic pull-in and operate modes, allows for automatic lock-up but requires a relatively long period of time in which to achieve full accuracy, both in the case of lock-up during startup of the phase-lock loop and in the case of recovery from a temporary loss of the external reference signal.
The long period of time required for lock-up is due to the wide gap between the bandwidth required for the pull-in mode and that required for high accuracy during the operation mode. Because of this wide gap, the alignment error at the end of the pull-in mode can be relatively large, requiring a relatively long time in the operate mode to achieve fine alignment.
Further, prior phase-locked loop systems are monitored for faults by an apparatus external to the signal processing algorithm of the phase-locked loop. When a fault condition defined by the occurrence of an error greater than a certain threshold is detected, the phase-locked loop is placed out of service. Thus, the occurrence of noise or other interference in the external reference signal or system hardware can affect system accuracy when it does not exceed the fault threshold, or result in unnecessary interruption when the threshold is exceeded.
Accordingly, the prior art is characterized by the inability to achieve a very accurate phase and frequency alignment fully automatically and quickly. Further, the prior art has failed to implement a high precision fault condition detection in the phase-locked loop environment.
The preferred embodiment of the present invention is implemented for use in synchronization of a digital transmission network or other environments requiring high accuracy phase-locked loop systems. An example of a network synchronization system to which the present invention is adapted, can be found in B. R. Saltzberg, and H. M. Zydney, "Digital Data System: Network Synchronization," THE BELL SYSTEM TECHNICAL JOURNAL, Vol. 54, No. 5, May-June 1975, pp. 879-792.
Background concerning phase-locked loops using digital data processors for signal processing and control functions in the network synchronization environment can be found in H. Fukinuki and I. Furukawa, "Intelligent PLL Using Digital Processing For Network Synchronization," IEEE TRANSACTIONS ON COMMUNICATIONS, Vol. COM-31, No. 12, December 1983. This article describes a digital processor controlled phase-locked loop typifying the prior art with a "pull-in" mode and an operating mode.
Examples of adaptive phase-locked loops are also provided in U.S. Pat. No. 4,513,429 by Roeder and U.S. Pat. No. 4,516,083 by Turney. The Roeder patent describes a system used for adaptive Doppler trackers. The Roeder patent provides a three-level adaptive phase-locked loop used for locking onto repetitive complex pulses. The three-level adaptive filter aids in the speed of lock and in the stability of the phase-locked loop. However, further improvements are desirable. The Turney patent describes an analog two-level phase-locked loop.